An Efficient Implementation of a Reversible Single Precision Floating Point Multiplier Using 4:3 Compressor

In this paper, we propose an efficient design of a reversible single precision floating point multiplier based on compressor. The single precision floating point multiplier requires the design of an efficient 24x24 bit integer multiplier. In the proposed architecture, the 24x24 bit multiplication operation is fragmented to nine parallel reversible 8x8 bit multiplication modules. In this paper, a new reversible design of the 24x24 bit multiplier has been proposed which has been optimized in terms of critical path delay and garbage outputs. In our design, the full adders are realized using synthesizable, less transistor count and low garbage output PRT-2 gates. Further, in our design for bias subtraction, PRT1 gate is used as a zero subtractor and one subtractor since it has less critical path delay. In this paper, sign operation, exponent addition, significand multiplication and normalization operations are implemented using reversible gates. VHDL is used to implement a technology-independent design.